1. Technical Field
The present invention relates in general to the field of data processing systems, particularly, memory within data processing systems. Still more particularly, the present invention relates to virtual memory management within data processing systems.
2. Description of the Related Art
Modern data processing systems typically utilize a virtual memory system to address very large amounts of memory, even though the main memory of the system encompasses a much smaller address space. Preferably, virtual memory systems include small storage capacity, rapid access memories (e.g., caches and random-access memory) and large storage capacity, slower access memories (e.g., hard disk drives). To maintain the illusion of a large, addressable memory space, recently-accessed data and instructions are stored in the small storage capacity, rapid access memories. Infrequently-accessed data and instructions are stored in large storage capacity, slower access memories and are only retrieved when requested by a data processing component, such as a processor.
To facilitate the retrieval and access of data within the virtual memory system, data and instructions are typically stored in discrete memory units. Such discrete memory units are typically referred to as “pages”. Because the physical location of a particular memory page may be located in any level of the virtual memory hierarchy, most modern data processing systems transfer or “page” memory pages between various levels of the virtual memory hierarchy as needed. While the various components of the data processing system submit requests to the virtual memory system for required memory pages utilizing a virtual memory address, a page frame table (PFT) is utilized to translate the virtual memory address to an actual physical address of the requested memory page.
Due to their very large size, page frame tables are typically stored in system memory and are often also paged. Those with skill in this art will appreciate that a method of minimizing the cost of main memory access time is to cache recently-accessed page table entries so the page table entry retrieval process is skipped if the current memory page request references the same page as a recently accessed page. Typically, the recently-accessed page table entry is saved in a special translation cache, known to those skilled in this art as a translation lookaside buffer (TLB).
Some modern data processing systems also support large pages to potentially increase memory coverage within the system memory. Such large pages require less memory to store metadata (e.g., page table entries within a page table) for a given memory range. They also require less overhead and can potentially improve performance for applications that have high memory demands. However, large pages may suffer from internal fragmentation, where a large amount of memory within a page is wasted or underutilized. Therefore, there is a need for a system and method for providing for more efficient processing of large memory pages in a data processing system.